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dual, 10 - bit nano dac with 2 ppm/c reference, spi interface data sheet ad5313r rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features low drift 2.5 v reference: 2 ppm/c typical tiny package: 3 mm 3 mm , 16 - lead lfcsp total unadjusted error (tue): 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1 % of fsr maximum high drive capability: 20 ma, 0.5 v from supply rails user selectable gain of 1 or 2 (gain pin) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility 50 mhz spi with readback or daisy chain low g litch: 0.5 nv -s ec robust 4 kv hbm and 1.5 kv ficdm esd rating s low power: 3.3 mw at 3 v 2.7 v to 5.5 v power supply ? 40c to +105c temperature range applications optical transceivers base station power amplifiers process control (plc i/o cards) industrial a utomation data acquisition systems functional block dia gram figure 1. general description the ad5313r , a member of the nano dac ? fam ily, is a low power, dual, 10 - bit buffered voltage out put digital - to - analog converter ( dac ) . the device include s a 2.5 v, 2 ppm/ c internal reference (enabled by default) and a gain select pin giving a full - scale output of 2.5 v ( gain = 1) or 5 v ( gain = 2). the ad5313r operate s from a single 2.7 v to 5.5 v supply, is guaranteed mono tonic by design, and exhibit s less t han 0.1% fsr gain error and 1.5 mv offse t error performance. the device is available in a 3 mm 3 mm lfcsp package and a tssop package. the ad5313r also incorporate s a power - on r eset ci rcuit and a rstsel pin that ensures that the dac outputs power up to zero scale or midscale and remain there until a valid write occurs . the part contains a per channel power - down feature that reduces the current consumption of the device to 4 a a t 3 v wh ile in power - down mode. the ad5313r employ s a versatile serial peripheral interface ( spi ) that operates at clock rates up to 50 mhz , and the device contain s a v logic pin that is in tended for 1.8 v/3 v/5 v logic . table 1 . related devices interface reference 12 - bit 10 - bit spi internal ad5687r n/a external ad5687 ad5313 1 i 2 c internal ad5697 r ad5338r 1 external n/a ad5338 1 1 the ad5313 r and the ad5313 are not pi n- to - pin or software compatible; likewise, the ad5338r and the ad5338 are not pin - to - pin or software compatible. product highlights 1. precision dc performance . total unadjusted error: 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum 2. low drift 2.5 v on- chip reference . 2 ppm/c typical temperature coeffi cient 5 ppm/c maximum temperature coefficient 3. two package options . 3 mm 3 mm , 16 - lead lfcsp 16- lead tssop sclk v logic sync sdin sdo input register dac register string dac a buffer v out a input register dac register string dac b buffer v out b v ref gnd v dd power- down logic power-on reset gain = 1/2 interface logic rstsel gain ldac reset ad5313r 2.5v reference 1 1254-001
ad5313r data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac charac teristics ........................................................................ 4 timing characteristics ................................................................ 5 daisy -c hain and readback timing characteristics ................ 6 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 16 theory of operation ...................................................................... 18 digital - to - analog converter (dac) ....................................... 18 transfer function ....................................................................... 18 dac architecture ....................................................................... 18 serial interface ............................................................................ 19 standalone operation ................................................................ 20 write and update command s .................................................. 20 daisy - chain operation ............................................................. 20 readback operation .................................................................. 21 power - down oper ation ............................................................ 21 load dac (hardware ldac pin) ........................................... 22 ldac mask register ................................................................. 22 hardware reset ( reset ) .......................................................... 23 reset select pin (rstsel) ........................................................ 23 internal reference s etup ........................................................... 23 solder heat reflow ..................................................................... 23 long - term temperature drift ................................................. 23 therma l hysteresis .................................................................... 24 applications information .............................................................. 25 microprocessor interfacing ....................................................... 25 ad5313r to adsp - bf531 interface ....................................... 25 ad5313r to sport interface .................................................. 25 layout guidelines ....................................................................... 25 galvanically isolated interface ................................................. 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 2/ 13 revision 0: initial version
data sheet ad5313r rev. 0 | page 3 of 28 specifications v dd = 2.7 v to 5.5 v; 1.8 v v logic 5.5 v; a ll specifications t min to t max , unless otherwise noted. r l = 2 k?; c l = 200 p f. table 2. parameter min typ max unit test conditions/comments static performance 1 resolution 10 bits relative accuracy 0.12 0.5 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design zero - code error 0.4 1.5 mv all 0 s loaded to dac register offset er ror + 0.1 1.5 mv full - scale error + 0.01 0.1 % of fsr all 1 s loaded to dac register gain error 0.02 0.1 % of fsr total unadjusted error 0.01 0.1 % of fsr external reference; gain = 2 ; tssop 0.2 % of fsr internal reference; gain = 1; tsso p offset error drift 2 1 v/c gain temperature coefficient 2 1 ppm of fsr/c dc power supply rejection ratio 2 0.15 mv/v dac code = midscale; v dd = 5 v 10 % dc crosstalk 2 2 v due to single - channel, full - scale output change 3 v/ma due to load current change 2 v due to powering down (per chan nel) output characteristics 2 output voltage r ange 0 v ref v gain = 1 0 2 v ref v gain = 2; see figure 29 capacitive load stability 2 nf r l = 10 nf r l = 1 k resistive load 3 1 k load regulation 80 v/ma 5 v 10%, dac code = midscale; ? 30 ma i out 30 ma 80 v/ma 3 v 10%, dac code = midscale; ? 20 ma i out 20 ma short - circuit current 4 40 ma load impedance at rails 5 25 see figure 29 power - up time 2.5 s coming out of power - down mode; v dd = 5 v ref erence output output voltage 6 2.4975 2.5025 v at ambient reference temperature coefficient 7 , 8 2 5 ppm/c see the terminology section output impedance 2 0.04 output voltage noise 2 12 v p -p 0.1 hz to 10 hz output voltage noise density 2 240 nv/hz at ambient; f = 10 khz, c l = 10 n f load regulation sourcing 2 20 v/ma at ambient load regulation sinking 2 40 v/ma at ambient output current load capability 2 5 ma v dd 3 v line regulation 2 100 v/v at ambient long - term stabilit y/drift 2 12 ppm after 1000 hours at 125 c thermal hysteresis 2 125 ppm first cycle 25 ppm additional cycles logic inputs 2 input current 2 a per pin input low voltage (v inl ) 0.3 v logic v input high voltage (v inh ) 0.7 v logic v pin capacitance 2 pf
ad5313r data sheet rev. 0 | page 4 of 28 parameter min typ max unit test conditions/comments logic outputs (sdo) 2 output low voltage (v ol ) 0.4 v i sink = 200 a output high volta ge (v oh ) v logic ? 0.4 v i source = 200 a floating state output capacitance 4 pf power requirements v logic 1.8 5.5 v i logic 3 a v dd 2.7 5.5 v gain = 1 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 9 0.59 0.7 ma internal reference off 1.1 1.3 ma internal reference on, at full scale all power - down modes 10 1 4 a ? 40 c to + 85 c 6 a ? 40 c to + 105 c 1 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv ; it exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity calculat e d using a reduced code range of 4 to 1020. 2 guaranteed by design and characterization ; not production tested. 3 channel a can have an output current of up to 30 ma. similarly, channel b can have an output current of up to 30 ma, up to a junction temperat ure of 110c. 4 v dd = 5 v . the device includes current limiting that is intended to protect the device during temporary overload conditions. junction temperature may be exc eed ed during current limit, but o peration above the specified max imum operation junc tion temperature can impair device reliability. 5 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 typical channel resistance of the output devices. for example , when sinking 1 m a, the minimum output voltage = 25 1 ma = 25 mv ( see figure 29). 6 initial accuracy presolder reflow is 750 v; o utput voltage includes the ef fects of preconditioning drift. see the i nternal reference setup section. 7 reference is trimmed and tested at two temperatures and is characteri z ed from ? 40c to +105c . 8 reference temperature coefficient is calculated as per th e box method. see the terminology section for more information. 9 inter face is inactive, both dacs are active, and dac outputs are unloaded. 10 both dacs are powered down. ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; 1.8 v v logic 5.5 v; all specifications t min to t max , unless otherwise noted. temperature range = ?40c to +105c, typical at 25c. guaranteed by design and characterization; not production tested. table 3 . parameter 1 min typ max unit test conditions/comments output voltage settling time 5 7 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital -to - analog glitch impulse 0.5 nv - sec 1 lsb change around major carry digital feedthrough 0.13 nv - sec digital cro sstalk 0.1 nv - sec analog crosstalk 0.2 nv - sec dac -to - dac crosstalk 0.3 nv - sec total harmonic distortion (thd) 2 ? 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density (nsd) 300 nv/ hz dac code = midscale, 10 khz; gain = 2 output noise 6 v p -p 0.1 hz to 10 hz s ignal - to - noise ratio (snr) 90 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz spurious free dynamic range ( sfdr ) 83 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz signal - to - noise - and - distortion ratio ( sinad ) 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz 1 see the terminology section. 2 digitally generated sine wave at 1 khz.
data sheet ad5313r rev. 0 | page 5 of 28 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2 . v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v, v ref = 2.5 v. all specifications t min to t max , unless otherwise noted. table 4. 1.8 v v logic < 2.7 v 2.7 v v logic 5.5 v parameter 1 min max min max unit description t 1 33 20 ns sclk cycle t ime t 2 16 10 ns sclk high t ime t 3 16 10 ns sclk low t ime t 4 15 10 ns sync to sclk falling edge setup t ime t 5 5 5 ns data setup t ime t 6 5 5 ns data hold t ime t 7 15 10 ns sclk falling e dge to sync rising e dge t 8 20 20 ns minimum sync high time (update single channel or both channels ) t 9 16 10 ns sync f all ing edge to sclk fall i gnore t 10 25 15 ns ldac pulse width l ow t 11 30 20 ns sclk falling e dge to ldac rising e dge t 12 20 20 ns sclk falling e dge to ldac falling e dge t 13 30 30 ns reset minimum pulse wid th l ow t 14 30 30 ns reset pulse activation t ime power -u p t ime 4.5 4.5 s time that is required to exit power - down mode and enter the normal mode of operation; 2 4th clock edge to 90% of dac midscale valu e with output unloaded 1 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v, 2.7 v v logic v dd . guaranteed by design and characterization; not production tested. figure 2 . serial write operation t 4 t 3 sclk sync sdin t 1 t 2 t 5 t 6 t 7 t 8 db23 t 9 t 10 t 11 ldac 1 ldac 2 t 12 1 asynchronous ldac update mode. 2 synchronous ldac update mode. reset t 13 t 14 v out x db0 1 1254-002
ad5313r data sheet rev. 0 | page 6 of 28 daisy -c hain and readback timing characteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 and figure 5 . v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v, v ref = 2.5 v. all specifications t min to t max , unless otherwise noted. v dd = 2.7 v to 5.5 v. table 5. 1.8 v v logic < 2.7 v 2.7 v v logic 5.5 v unit parameter 1 min max min max desc ription t 1 66 40 ns sclk cycle t ime t 2 33 20 ns sclk high t ime t 3 33 20 ns sclk low t ime t 4 33 20 ns sync to sclk falling edge t 5 5 5 ns data setup t ime t 6 5 5 ns data hold t ime t 7 15 10 ns sclk falling e dge to sync rising e dge t 8 60 30 ns minimum sync high time t 9 60 30 ns minimum sync high t ime t 10 36 25 ns sdo data v alid from sclk rising e dge t 11 15 10 ns scl k falling e dge to sync rising e dge t 12 15 10 ns sync rising edge to sclk rising e dge 1 maximum sclk frequency is 25 mhz or 15 mhz at v dd = 2.7 v to 5.5 v, 1.8 v v logic v dd . guaranteed by design and characterization; not production tested. circuit and timing diagrams figure 3. load circuit for digital output (sdo) timing specifica tions figure 4 . daisy - chain timing diagram 200a i ol 200a i oh v oh (min) to output pin c l 20pf 1 1254-003 t 4 t 5 t 6 t 8 sdo sdin sync sclk 48 24 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n + 1 input word for dac n db 0 t 11 t 12 t 10 1 1254-004
data sheet ad5313r rev. 0 | page 7 of 28 figure 5 . readback timing diagram sync t 8 t 6 sclk 24 1 24 1 t 9 t 4 t 2 t 7 t 3 t 1 db23 db0 db23 db0 sdin nop condition input word specifies register to be read t 5 db23 db0 db23 db0 sdo selected register data clocked out undefined t 10 1 1254-005
ad5313r data sheet rev. 0 | page 8 of 28 absolute maximum rat ings t a = 25 c, unless otherwise noted. table 6. parameter rating v dd t o gnd ? 0.3 v to +7 v v logic to gnd ? 0.3 v to +7 v v out to gnd ? 0.3 v to v dd + 0.3 v v ref to gnd ? 0.3 v to v dd + 0.3 v digital input voltage to gnd ? 0.3 v to v logic + 0.3 v operating temperature range ? 40c to +10 5 c storage temperature range ? 65 c to + 150 c junction temperature 125c 16 - lead tssop, ja thermal impedance , 0 airflow (4- layer board) 1 12.6 c/w 16 - lead lfcsp, ja thermal impedance , 0 airflow (4 - layer board) 70 c/w reflow soldering peak temperature, pb free (j - std - 020) 260 c esd 1 4 kv ficdm 1.5 kv 1 human body model (hbm) classification. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condi tions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5313r rev. 0 | page 9 of 28 pin configurations and function descri ptions figure 6. 16 - lead lfcsp pin configuration figure 7. 16 - lead tssop pin configuration table 7 . pin function descriptions pin no. mnemonic description lfcsp tssop 1 3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 2 4 gnd ground reference point for all circuitry on the ad5313r . 3 5 v dd power supply input. the ad5313r can b e operated from 2.7 v to 5.5 v. decouple the supply with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 6 nc no connect. do not connect to this pin. 5 7 v out b analog output voltage from dac b . t he output amplifier has rail -to - rail operation. 6 8 sdo serial data output. sdo c an be used to daisy - chain a number of ad5313r devices together , or it can be used for readback. the serial data is transferred o n the rising edge of sclk and is valid on the falling edge of the clock. 7 9 ldac ldac can be operated in two modes: asynchronous and synchronous . pulsing this pin low allows either or both dac registers to be updated if the input registers have new data; both dac outputs can be updated simultaneously. this pin can also be tied permanently low. 8 10 gain gain select . when this pin is tied to gnd , both dac s output a span from 0 v to v ref . if this pin is tied to v lo gic , both dac s output a span of 0 v to 2 v ref . 9 11 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 10 12 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 50 mhz. 11 13 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, d ata is transferred in on the falling edges of the next 24 clocks. 12 14 sdin serial data input. this device has a 24 - bit input shift register. data is clocked into the register on the falling edge of the serial clock input. 13 15 reset asynchronous reset input. the reset input i s falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or mid scale , depending on the state of the rstsel pin. 14 16 rstsel power - on reset select . tying this pin to gnd powers up both dacs to zero scale. tying this pin to v logic powers up both dacs to midscale. 15 1 v ref reference voltage. the ad5313r has a common reference pin. when using the internal reference, this is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference output. 16 2 nc no connect. do not c onnect to this pin. 17 n/a epad exposed pad. the exposed pad must be tied to gnd. 12 11 10 1 3 4 sdin sync sclk 9 v logic v out a v dd 2 gnd nc 6 sdo 5 v out b 7 ldac 8 gain 16 nc 15 v ref 14 rstsel 13 reset top view (not to scale) ad5313r notes 1. the exposed pad must be tied to gnd. 2. nc = no connect. do not connect to this pin. 1 1254-006 1 2 3 4 5 6 7 8 nc v out a gnd v out b nc v dd v ref sdo 16 15 14 13 12 11 10 9 reset sdin sync gain ldac v logic sclk rstsel notes 1. nc = no connect. do not connect to this pin. top view (not to scale) ad5313r 1 1254-007
ad5313r data sheet rev. 0 | page 10 of 28 typical performance characteristics figure 8. internal reference voltage vs. temperature figure 9. refer ence ou tput temperature drift histogram figure 10 . reference long- term stability/drift figure 11 . internal reference noise spectral density v s. frequency figure 12 . internal reference noise , 0.1 hz to 10 hz figure 13 . internal reference voltage vs. load current ?40 ?20 0 20 40 60 80 100 120 v ref (v) temperature (c) device 1 device 2 device 3 device 4 device 5 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 v dd = 5v 1 1254-008 90 0 10 20 30 40 50 60 70 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 number of units temperature drift (ppm/c) v dd = 5v 1 1254-010 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours v dd = 5.5v 1 1254-0 11 1600 0 200 400 600 800 1000 1200 1400 10 100 1k 10k 100k 1m nsd (nv/ hz) frequency (mhz) v dd = 5v t a = 25c 1 1254-012 ch1 10v m1.0s a ch1 160mv 1 t v dd = 5v t a = 25c 1 1254-013 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 ?0.005 ?0.003 ?0.001 0.001 0.003 0.005 v ref (v) i load (a) v dd = 5v t a = 25c 1 1254-014
data sheet ad5313r rev. 0 | page 11 of 28 figure 14 . internal reference voltage vs. supply voltage figure 15 . integral nonli nearity (inl) vs. code figure 16 . differential nonlinearity (dnl) vs. code figure 17 . inl error and dnl error vs. temperature figure 18 . inl error and dnl error vs. v ref figure 19 . inl error and dnl error vs. supply voltage 2.5002 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v ref (v) v dd (v) d1 d3 d2 t a = 25c 1 1254-015 1 1254-016 0.5 ?0 .5 ?0 .3 ?0 .1 0.1 0.3 0 15 6 31 2 46 8 62 5 78 1 93 8 inl (lsb) code 1 1254-017 dn l (lsb) code 0.5 ?0 .5 ?0 .3 ?0 .1 0.1 0.3 code 0 15 6 31 2 46 8 62 5 78 1 93 8 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 110 60 10 error (lsb) temperature (c) inl dnl v dd = 5v t a = 25c reference = 2.5v 1 1254-018 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 5.04.54.03.53.02.52.01.51.00.5 error (lsb) v ref (v) inl dnl v dd = 5v t a = 25c reference = 2.5v 1 1254-019 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 2.7 5.2 4.7 4.2 3.7 3.2 error (lsb) supply voltage (v) inl dnl v dd = 5v t a = 25c reference = 2.5v 1 1254-020
ad5313r data sheet rev. 0 | page 12 of 28 figure 20 . gain error and full - scale error vs. temperature figure 21 . zero - code error and offset error vs. tempera ture figure 22 . gain error and full - scale error vs. supply figure 23 . zero - code error and offset error vs. supply figure 24 . total unadjusted error vs. temperature f igure 25 . total unadjusted error vs. supply voltage , gain = 1 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temperature (c) gain error full-scale error v dd = 5v t a = 25c reference = 2.5v 1 1254-021 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?20 0 20 40 60 80 100 120 error (mv) temperature (c) offset error zero-code error v dd = 5v t a = 25c reference = 2.5v 1 1254-022 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 2.7 5.2 4.7 4.2 3.7 3.2 error (% of fsr) supply voltage (v) gain error full-scale error v dd = 5v t a = 25c internal reference = 2.5v 1 1254-023 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.7 5.2 4.7 4.2 3.7 3.2 error (mv) supply voltage (v) zero-code error offset error v dd = 5v t a = 25c internal reference = 2.5v 1 1254-024 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?4 0 ?2 0 0 20 40 60 8 0 10 0 12 0 tot al unadju sted e rr or (% o f f sr) tempe ra t ur e (c) v dd = 5v t a = 25 c inte rna l refere nc e = 2.5 v 1 1254-025 0.10 0.08 0.06 0.04 0.02 0 ?0 .02 ?0 .04 ?0 .06 ?0 .08 ?0 .10 2.7 5.2 4.7 4.2 3.7 3.2 tot al unadju sted e rr or (% o f f sr) supply v olt age (v) v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1254-026
data sheet ad5313r rev. 0 | page 13 of 28 figure 26 . total unadjusted error vs. code figure 27 . i dd histogram with external reference, v dd = 5 v figu re 28 . i dd histogram with internal reference, v ref = 2.5 v , gain = 2 figure 29 . headroom/footroom vs. load current figure 30 . source and sink capability at v dd = 5 v figure 31 . source and sink capability at v dd = 3 v 0 ?0 .01 ?0 .02 ?0 .03 ?0 .04 ?0 .05 ?0 .06 ?0 .07 ?0 .08 ?0 .09 ?0 .10 0 1000 0 2000 0 3000 0 4000 0 5000 0 6000 0 6553 5 tot al unadju sted e rr or (% o f f sr) code v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1254-027 25 20 15 10 5 0 540 560 580 600 620 640 h it s v dd = 5v t a = 25 c exte rnal refere nc e = 2.5v 1 1254-028 i dd fu ll s ca le (v) 30 25 20 15 10 5 0 100 0 102 0 104 0 106 0 108 0 110 0 112 0 114 0 h it s i dd fu ll s ca le (v) v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1254-029 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 v out (v) load current (ma) sourcing 2.7v sourcing 5v sinking 2.7v sinking 5v 1 1254-030 1 1254-031 7 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) full scale one-quarter scale midscale three-quarter scale zero scale v dd = 5v t a = 25c gain = 2 internal reference = 2.5v 1 1254-032 5 ?2 ?1 0 1 2 3 4 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) v dd = 3v t a = 25c external reference = 2.5v gain = 1 full scale one-quarter scale m idscale three-quarter scale zero scale
ad5313r data sheet rev. 0 | page 14 of 28 figure 32 . supply current vs. temperature figure 33 . digital -to- analog glitch impulse figure 34 . 0.1 hz to 10 hz output noise plot, external reference figure 35 . 0.1 hz to 10 hz output noise plot, 2.5 v internal reference figure 36 . noise spectral density figure 37 . total harmonic distortion at 1 khz 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?4 0 11 0 60 10 supply curr ent ( ma ) tempe ra t ur e (c) fu ll s ca le zero code exte rna l refere nc e , f u ll -s ca le 1 1254-033 2.4988 2.5008 2.5003 2.4998 2.4993 0 12 8 10 4 6 2 v out (v) time (s) channel b t a = 25c v dd = 5.25v reference = 2.5v positive major code transition energy = 0.227206nv-sec 1 1254-034 ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c reference = 2.5v 1 1254-035 ch1 10 v m1.0s a ch1 802m v 1 t v dd = 5v t a = 25 c inte rna l referenc e = 2.5v 1 1254-036 0 20 0 40 0 60 0 80 0 100 0 120 0 140 0 160 0 10 1m 100 k 1k 10 k 10 0 nsd (nv/ hz) freque nc y (hz) fu ll s ca le mids ca le zero s ca le v dd = 5v t a = 25 c inte rna l refere nc e = 2.5v 1 1254-037 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 20000 16000 8000 12000 4000 2000 18000 10000 14000 6000 thd (dbv) frequency (hz) v dd = 5v t a = 25c reference = 2.5v 1 1254-038
data sheet ad5313r rev. 0 | page 15 of 28 figure 38 . multiplying bandwidth, ext ernal reference = 2.5 v, 0.1 v p-p, 10 khz to 10 mhz ?60 ?50 ?40 ?30 ?20 ?10 0 10k 10m 1m 100k bandwidth (db) frequency (hz) v dd = 5v t a = 25c reference = 2.5v, 0.1v p-p 1 1254-039
ad5313r data sheet rev. 0 | page 16 of 28 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figure 15 . differenti al nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mo notonic by design. a typical dnl vs. code plot is shown in figure 16 zero - code error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. th e zero - code error is always positive in the ad5313r because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is expressed in mv. a plot of zero - code error vs. temperature is shown in figure 21 . full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output shou ld be v dd ? 1 lsb. full - scale error is expressed in percent of full - scale range (% of fsr) . a plot of full - scale error vs. temperature is shown in figure 20 . gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal and is expressed as % of fsr. offset error drift offset error drift is a measurement of the change in offset error with a change in temperature. it is expressed in v/c. g ain te mp erature coefficient gain temperature coefficient is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) e xpressed in mv in the linear region of the transfer function. offset error is measured on the ad5313r with code 8 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (ps rr) psrr indicates how the output of the dac is affected by change s in the supply voltage. it is the ratio of the change in v out to a change in v dd for the full - scale output of the dac. it is measured in mv/v . v ref is held at 2 v, and v dd is varied by 10% . output voltage settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input change and is measured from the rising edge of sync . digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv -s ec and is measured when the digit al input code is changed by 1 lsb at the major carry transition , that is, 0x7fff to 0x8000 (see figure 33). digital feedthrough digital feedthrou gh is a measure of the impulse injected into the analog output of the dac fro m the d igital inputs of the dac; it is measured when the dac output is not updated. it is specified in nv -s ec and measured with a full - scale code change on the data bus, that is, from all 0 s to all 1 s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density (nsd) nsd is a measurement of the internally generated random noise. random noise is characterized as a spectral density . it is measured , in nv/hz, by loading the dac to midscale and measuring noise at the output . a plot of noise spectral density is shown in figure 36. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a chang e in the output of another dac. it is measured with a full - scale output change (or soft power - down and power - up) on one dac while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the im pact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change ( all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and expressed in nv - sec. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output o f another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch i s expressed in nv -s ec .
data sheet ad5313r rev. 0 | page 17 of 28 dac -to - dac crosstalk dac - to - dac c rosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa) , using the write to and update command s while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv -s ec . multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) t hd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics pre sent on the dac output. it is measured in db. voltage reference temperature coefficient voltage r eference tc is a measure of the change in the reference output voltage with a change in temperature. the reference tc is calculated using the box method, which defines the tc as the maximum change in the reference output over a given tempera - ture range expressed in ppm/c , as follows: 6 10 ? ? ? ? ? ? ? ? ? = temprange v vv tc refnom refmin refmax where: v refmax is the maximum reference output measured over the total temperature range. v refmin is the m inimum reference output measured over the total temperature range. v refnom is the nom inal reference output voltage, 2.5 v. temprange is the specified temperature range of ?40c to +105c.
ad5313r data sheet rev. 0 | page 18 of 28 theory of operation digital - to - analog converter (dac) t he ad5313r is a dual 10 - bit, s erial input, voltage output dac with an internal reference. the part operate s from supply voltages of 2.7 v to 5.5 v. data is written to the ad 5313r in a 24- bit word format via a 3 - wire serial interface. th e ad5313r incorporate s a power - on reset circuit to ensure that the dac output powers up to a known output state. the device also has a software po wer - down mode that reduces the typical current consumption to 4 a. transfer function the internal reference is on by default. to use an external reference , only a nonreference option is available. because the input coding to the dac is straight binary, th e ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n ref out d gainvv 2 where: gain is the output amplifier gain and is set to 1 by default. it can be set to 1 or 2 using the gain select pin. when th e gain pin is tied to gnd, both dac outputs have a span from 0 v to v ref . if the gain pin is tied to v logic , both dac s output a span of 0 v to 2 v ref . d is the decimal equivalent of the binary code that is loaded to the dac register as follows: 0 to 1,024 for the 10 - bit device . n is the d ac resolution. dac architecture the dac architecture consists of a string dac followed by an output amplifier. figure 39 shows a block diagram of the dac arc hitecture. figure 39 . single dac channel archi tecture block diagram the resistor string structure is shown in figure 40 . it is a string of resistors, each of value r. the code loaded to the dac register determines the node on the string where the voltage is to be tapped off a nd fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. figure 40 . resistor string stru cture internal reference the ad5313r on - chip reference is on at power - up but can be disabled via a write to a control register. see the i nternal reference setup section for details. t he ad5313r ha s a 2.5 v, 2 ppm/c reference , giving a full - scale output of 2.5 v or 5 v, depending on the state of the gain pin. the internal reference associated with the device is available at the v ref pin. th is buffe red reference is capable of driving external loads of up to 10 ma. output amplifier s the output buffer amplifier can generate rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on the value of v ref, the gain pin, the offset error, and the gain error. the gain pin selects the gain of the output, as follows: ? if the gain pin is tied to gnd, both dac outputs have a gain of 1, and the output range is 0 v to v ref . ? if the gain pin is tied to v logic , bo th dac outputs have a gain of 2, and the output range is 0 v to 2 v ref . the se amplifier s are capable of driving a load of 1 k? in parallel with 2 nf to gnd. the slew rate is 0.8 v/s with a ? to ? scale settling time of 5 s. input register 2.5v ref dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 1 1254-040 r r r r r to output amplifier v ref 1 1254-041
data sheet ad5313r rev. 0 | page 19 of 28 serial interface t he ad5313r ha s a 3 - wire serial interface ( sync , sclk, and s din) that is compatible with spi, qspi ? , and microwire ? interface stan dards as well as most dsps. see figure 2 for a timing diagram of a typi cal write sequence. the ad5313r contains an sdo pin that allows the user to daisy - chain multiple devices together (see the daisy - chain operation section) or r ead back data . input shift register the input shift register of the ad5313r is 24 bits wide, and d ata is loaded msb first (db23). the first four bits are the command bits ( c3 to c0 , as listed in table 9 ), followed by the 4 - bit dac address bits listed in table 8 (dac b, two dont care bits set to 0, and dac a ). finally, the data - word complete s the input shift register. the data - word comprises 10 - bit input code, followed by six dont care bits (see figure 41 ). these data bits are transfe rred to the input shift register on the 24 falling edges of sclk and are updated on the rising edge of sync . comm ands can be ex ecuted on individual dac channels or on both dac channels, depending on the address bits selected . table 8 . address commands address (n) selected dac channel dac b 0 0 dac a 0 0 0 1 dac a 1 0 0 0 dac b 1 0 0 1 dac a and dac b table 9 . command definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n (dependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software reset (power - on reset) 0 1 1 1 internal reference setup register 1 0 0 0 set up dcen register (daisy - chain en able) 1 0 0 1 set up r eadback register (readback enable) 1 0 1 0 reserved reserved 1 1 1 1 reserved figure 41 . input shift register content address bits comm a nd bits dac b 0 0 dac a d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x c3 c2 c1 c0 db23 (msb) db0 (lsb) data bits 1 1254-042
ad5313r data sheet rev. 0 | page 20 of 28 standalone operation the write sequence begins by bringing the sync line low. data from the sdin line is clocked into the 24 - bit input shift regis ter on the falling edge of sclk. after the last of 24 data bits is clocked in , sync is brought high. the programmed function is then executed; t hat is, an ldac - dependent change in dac register contents and/or a change in the mode of operation occurs . if sync is taken high before the 24 th clock, it is considered a valid frame, and invalid data may be loaded to the dac. sync must be brought high for a minimum of 20 n s (single channel, see t 8 in figure 2 ) before the next write sequence so that a falling edge of sync can initiate the next write sequen ce. idle sync at the rails between write sequences for an even lower power operation of the part. the sync line is kept low for 24 falling edges of sclk, and the dac is updated on the rising edge of sync . when the data has been transferred into the input register of the addressed dac, both dac registers and outputs can be updated by taking ldac low while the sync line is high. write and update com mands write to input register n (dependent on ldac ) command 0001 allows the user to write to the dedicated input register of each dac individually. when ldac is low, the input register is transparent (if not controlled by the ldac mask register). update dac register n with contents of input register n command 0010 loads the dac registers/outputs with the contents of the input registers selected and update s the dac outputs directly. write to and update dac channel n (independ ent of ldac ) command 0011 allows the user to write to the dac registers and update the dac outputs directly. daisy - chain operation for systems that contain several dacs , the sdo pin can be used to daisy - chain several devices together. sdo is enabled through a software executable daisy - chain enable (dcen) command. command 1000 is reserved for this dcen function (see table 9 ). the daisy - chain mode is enabled by setting bit db 0 in the dcen register. the default set ting is standalone mode, where db0 (lsb) = 0. table 10 shows how the state of the bit corresponds to the mode of operation of the device. table 10 . daisy - chain enable ( dcen) register db0 (lsb) description 0 standalone mode (default) 1 dcen mode figure 42 . daisy - chaining multiple ad5313r devices the sclk pin is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the s din input on the next dac in the chain, a daisy - chain interface is constructed. ea ch dac in the system requires 24 clock pulses. t herefore, the total numb er of clock cycles must equal 24 n, where n is the total number of devices that are updated. if sync is taken high at a clock that is not a multiple of 24, it is considered a valid frame, and invalid data may be loaded to the dac. when the serial transfer to all devices is complete, sync is taken high . t his latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the serial clock can be continuous or a gated clock. a continuous sclk source can be used only if sync can be held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. 68hc11* miso sdin sclk mosi sck pc7 pc6 sdo sclk sdo sclk sdo sdin sdin sync sync sync ldac ldac ldac ad5313r ad5313r ad5313r *additional pins omitted for clarity. 1 1254-043
data sheet ad5313r rev. 0 | page 21 of 28 r eadback operation readback mode is invoked through a software executable readback command. if the sdo output is disabled via the daisy - chain mode disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again. command 1001 is reserved for the readback function. this com - mand, in association with selecting one of the address bits , dac b or dac a , determines the register to be read. note that only one dac register can be selected durin g readback. the remaining three address bits ( which includes the two dont care bits) must be set to logic 0 . the remaining data bits in the write sequence are ignored. if more than one address bit is selected or no address bits are selected , dac channel a is read back by default. during the next spi write, the data appearing on the sdo output contains the data from the previously addressed register. for example, to read back the dac register for channel a, implement the following sequence: 1. write 0x900000 t o the ad5313r input register. this setting configures the part for read mode with the channel a dac register selected. note that all data bits , db15 to db0 , are dont care bits. 2. follow this write operation with a second write, a nop condition, 0x000000. during this write, the data from the register is clocked out on the sdo line . db23 to db20 contain undefined data , and the last 16 bits contain the db 19 to db 4 dac register contents. power - down operation t he ad5313r contain s three separate power - down modes. command 0100 controls the power - down function (see table 9 ). these power - down modes are software - programmable by setting eight bits, bit db7 to bit db0 , in the input shift register. there are two bits associated with each dac channel. table 11 explains how the state of the two bits corresponds to the mode of operation of the device. table 11 . modes of operation operating mode pdx 1 pdx 0 normal operation mode 0 0 power - down modes 1 k to gnd 0 1 100 k to gnd 1 0 three - state 1 1 either dac or both dacs (dac a and dac b ) can be powered down to the selected mode by setting the corresponding bits . see table 12 for the contents of the input shift reg ister during the power - down/power - up operation. when both bit pdx1 and bit pdx0 (where x is the channel that is selected ) in the input shift register are set to 0, the ad5313r works normally , with a normal powe r consumption of 4 ma at 5 v. however, for the three power - down modes of the ad5313r , the supp ly current falls to 4 a at 5 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values . this switchover has the advantage that the output impedance of the part is known while the part is in power - down mode. the three power - down options are as follows : ? t he output is connected internally to gnd through a 1 k? resistor. ? the output is connected internally to gnd through a 100 k? resistor. ? the output is left open - circuited (three - state). the output stage is illustrated in figure 43. figure 43 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power - down mode is activated. however, the contents of the dac register are unaffected when in power - down, and t he dac register can be updated while the device is in power - down mode. the time that is required to exit power - down is typically 4.5 s for v dd = 5 v. to further reduce the current consumption, the on - chip reference can be powered off (see the i nternal reference setup section). table 12 . 24- bit input shift regist er contents of power - down/power - up operation 1 db23 (msb) db2 2 db2 1 db20 db19 to db16 db15 to db8 db7 db6 db 5 db 4 db 3 db 2 db 1 db 0 (lsb) 0 1 0 0 x x pdb1 pdb0 1 1 1 1 pda1 pda0 command bits (c3 to c 0) address bits; dont care power - down, select dac b set t o 1 set to 1 power - down, select dac a 1 x = do nt care. resis to r ne two rk v out x da c p ow er-d ow n ci rcu it ry amp lifi er 1 1254-044
ad5313r data sheet rev. 0 | page 22 of 28 load dac ( hardware ldac pin ) the ad5313r dacs have double buffered interfaces consisting of two banks of registers: input registers and dac regis ters. the user can write to any combination of the input registers. updates to the dac register are controlled by the ldac pin. figure 44 . simplified diagram of input loading circuitry for a single dac instanta neous dac updating ( ldac held low ) ldac is held low while data is clocked into the input register using command 0001. both t he addressed input register and the dac register are updated on the rising edge of sync , and then the output begins to change (see table 14 and table 15). deferred dac updating ( ldac pulsed low) ldac is held high while d ata is clocked into the input register using command 0001 . both dac outputs are asynchronously updated by taking ldac low after sync is taken high. the update then occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for a software ldac mask function, which allows t he a ddress bits to be ignored. a write to the dac using command 0101 loads the 4 - bit ldac mask r egister (db3 to db0). the default setting for each channel is 0; that is, the ldac pin works normally. setting the selected bit to 1 forces the dac channel to ignore transitions on the ldac pin, regardless of the st ate of the hardware ldac pin. this flexibility is useful in applications where the user wishes to select which channels respond to the ldac pin. the ldac mask register gives the user extra flexibility a nd control over the hardware ldac pin (see table 13 ). setting an ldac bit (db3, db0) t o 0 for a dac channel means that the update of this channel is controlled by the hardware l dac pin. table 13. ldac overwrite definition load ldac register ldac bits (db3, db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels update and override the ldac pin. dac channels see the ldac pin as set to 1. 1 x = dont care. table 14 . 24- bit input shift register contents for ldac operation 1 db 23 (msb) db 22 db 21 db 20 db19 db18 db17 db16 db 15 to db4 db 3 db 2 db 1 db 0 (lsb) 0 0 0 1 x x x x x dac b 0 0 dac a command bits (c 3 to c 0 ) address bits , d ont care dont care setting the ldac bit to 1 ov errides the ldac pin 1 x = dont care. table 15. write commands and ldac pin truth table 1 command description hardware ldac pin state input register contents dac register contents 0001 write to input register n (d ependent on ldac ) v logic data update no change (no update) gnd 2 data update data update 0010 upda te dac register n with contents of input register n v logic no change updated with input register contents gnd no change updated with input register contents 0011 write to and update dac channel n v logic data update data update gnd data update data update 1 a high - to - low hardware ldac pin transition always updates the contents of the dac register with the contents of the input register on channels that are n ot masked (blocked) by the ldac mask register. 2 when the ldac pin is permanently tied low, the ldac mask bits are ignored. sy nc sclk v out x dac regist er interface l og ic outpu t a mp lifi er ldac sdo sdin v ref input regist er 10-bit dac 1 1254-045
data she et ad5313r rev. 0 | page 23 of 28 hardware reset ( reset ) reset is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user selectable via the power - on reset select pin (rstsel). reset must be kept low for a minimum amount of time to complete the operation (see figure 2 ). when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the reset pin is low. there is a lso a software executable reset function that resets the dac to the power - on reset code. command 0110 is designated for this software reset function (see table 9 ). any events on ldac or reset du ring a power - on reset are ignored. reset select pin (rs tsel) th e ad5313r contain s a power - on reset circuit that controls the output voltage during power - up. when the rstsel pin is connected low (to gnd), the ou tput powers up to zero scale. note that this is outsi de the linear region of the dac. when the rstsel pin is connected high (to v logic ), v out x powers up to midscale. the output remains powered up at this level until a valid wri te sequence is sent to the da c. i nternal reference se tup command 0111 is reserved for setting up the internal reference (see table 9 ). b y default , t he on - chip reference is on at power - up. to reduce the supply current , this reference can be turned off by setti ng the software - programmable bit, db0, as shown in table 17 . table 16 shows how the state of the bit corresponds to the mode of opera tion. table 16 . internal reference set up regis ter internal reference setup register (db0) action 0 reference on (default) 1 reference off solder heat reflow as with all ic reference voltage circuits, the reference value experience s a shift induced by the soldering process. a nalog devices, i nc., p erforms a reliability test, called precondition, that mimics the effect of soldering a device to a board. the output voltage specification that is listed in table 2 includes the effect of this reliability test. figure 45 shows the effect of solder heat reflow (shr) as measured through the reliability test (precondition). figure 45 . shr reference voltage shift long- term temperature dri ft figure 46 shows the change in v ref value after 1000 h ou rs in life test at 150 c. figure 46 . reference drift through to 1000 h ou rs table 17 . 24- bit input s hift register contents for internal reference setup command 1 db23 (msb) db2 2 db2 1 db20 db19 db18 db17 db16 db15 to db1 db0 (lsb) 0 1 1 1 x x x x x 0 or 1 command bits (c3 to c 0) address bits (a3 to a0) dont care reference setup register 1 x = dont care 60 0 10 20 30 40 50 2. 49 8 2. 49 9 2. 50 0 2. 50 1 2. 50 2 h it s v ref (v) posts ol der heat re flo w pres ol der heat re flo w 1 1254-046 60 0 10 20 30 40 50 2. 49 8 2. 49 9 2. 50 0 2. 50 1 2. 50 2 h it s v ref (v) 0 hour 168 ho ur s 500 ho ur s 1000 ho ur s 1 1254-047
ad5313r data sheet rev. 0 | page 24 of 28 thermal hysteresis thermal h ysteresis is the voltage difference induced on the ref - erence voltage by sweeping the temperature from ambient to cold, then to hot, and then back to ambient. thermal h ysteresis data is shown in figure 47 . it is measured by sweeping the temperature from ambient to ? 40 c, next to + 105 c, and then returning to ambient. the v ref delta is then measured between the two ambient measurements and shown in blue in figure 47 . the same temperature sweep and measure - ments are immediately repeated, and the results are shown in red in figure 47 . figure 47 . thermal hysteresis 9 8 7 6 5 4 3 2 1 0 50 0 ?5 0 ?10 0 ?15 0 ?20 0 h it s dis to r tio n ( pp m) fi rs t t empe ra t ur e s weep s ub sequ en t t empe ra t ur e sw eeps 1 1254-048
data she et ad5313r rev. 0 | page 25 of 28 applications informa tion microprocessor inter facing microproc essor interfacing to the ad5313r is achieved via a serial bus using a standard protocol that is compatible with dsp processors and microcontrollers. the communications channel requires a 3 - wire or 4 - wire interface consisting of a clock signal, a data signal, and a syn chron ization signal. the device require s a 24- bit data - word with data valid on the rising edge of sync . ad5313r to adsp - bf531 interface the spi inte rface of the ad5313r is designed to be easily connected to industry - standard dsps and microcontrollers. figure 48 shows the ad5313r connec ted to an analog devices blackfin? dsp. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5313r . figure 48 . ad5313r to adsp - bf531 interface ad5313r to sport interface the analog devices adsp - bf527 has on e sport serial port. figure 49 shows how one sport interface can be used to control the ad5313r . figure 49 . ad53 13r to sport interface layout guidelines in any circuit where accuracy is important, careful considera - tion of the power supply and ground return layout helps to ensure the rated performance. design t he pcb on which the ad5313r is mounted such that the ad5313r lies on the analog plane. provide the ad5313r with ample supply bypassing of 10 f in parallel with 0.1 f on ea ch supply, located as close to the package as possible, ideally right up against the device. the 10 f capa - citors are of the tantalum bead type. use a 0.1 f capacitor with low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems wh ere there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the ad5313r has an exposed paddle beneath the device. connect this p addle to the gnd supply for the part. for optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the exposed paddle on the bottom of the pack age to the corresponding thermal land paddle on the pcb. design thermal vias into the pcb land paddle area to further improve heat dissipation. the gnd plane on the device can be increased (as shown in figure 50 ) to provide a nat ural heat sinking effect. figure 50 . paddle connection to board galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being contr olled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. the i coupler? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5313r makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 51 shows a 4 - channel isolated interface to the ad5313r using an adum1400 . for more information, visit http://www.analog.com/icouplers . figure 51 . isolated interface adsp-bf531 sync spiselx sclk sck sdin mosi ldac pf9 reset pf8 ad5313r 1 1254-049 adsp-bf527 sync sport_tfs sclk sport_tsck sdin sport_dto ldac gpio0 reset gpio1 ad5313r 1 1254-050 ad5313r gnd plane board 1 1254-051 encode serial clock in controller adum1400 1 serial data out sync out load dac out decode to sclk to sdin to sync to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 1 additional pins omitted for clarity. 1 1254-052
ad5313r data sheet rev. 0 | page 26 of 28 outline dimensions figure 52 . 16 - lead lead frame chip scale package [ lfcsp _wq ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters figure 53 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 resolution temperature range accuracy reference tempco (ppm/ c) package description package option branding ad5313r bcpz -rl 7 10 bits ? 40 c to + 105 c 2 lsb inl 5 (max) 16 - lead lfcsp_w q cp -16 -22 dkz ad5313r bruz 10 bits ? 40c to +105c 2 lsb inl 5 (max) 16 - lead tssop ru -16 ad5313r bruz -rl7 10 bits ? 40c to +105c 2 lsb inl 5 (max) 16- lead tssop ru -16 1 z = rohs compliant part. 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic at or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic at or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab
data she et ad5313r rev. 0 | page 27 of 28 notes
ad5313r data sheet rev. 0 | page 28 of 28 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11254 -0- 2/13(0)

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